OPENLPPOL-EVB【PDF 4/36 页】BOARD EVAL OPEN-LOOP POL

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Si85xx

1. Electrical Specifications

Table 1. Electrical Specifications

T A = –40 to +125 oC (typical specified at 25 oC), VDD = 3 V (±10%) to 5 V (±10%), f = 400 kHz, unless specified

Parameter

Supply Voltage (V DD )

Supply Current

Conditions

Fully enabled,

Min

2.7

—

Typ

—

4

Max

5.5

7

Unit

V

mA

input frequency = 1 MHz

Undervoltage Lockout (V UVLO )

Undervoltage Lockout Hysteresis

2.1

—

2.3

100

2.5

—

V

mV

(V HYST )

Logic Input HIGH Level

Logic Input LOW Level

Reset Time (t R )

MODE, R1, R2, R3, R4 inputs

(TTL compatible)

Time for 5% initial accuracy

2.0

—

150

—

—

—

—

0.8

—

V

V

ns

Reset Time Resistor

Range 1

15

—

2500

k ?

R1, R2, R3, R4 Input Rise Time (t RR )

R1, R2, R3, R4 Input Fall Time (t FR )

Measurement Watchdog Timeout (t WD )

—

—

30

—

—

50

30

30

80

ns

ns

μs

Series Input Resistance

Series Inductance

Measured from IIN to IOUT

Measured from IIN to IOUT

—

—

1.3

2

—

—

m ?

nH

Input/Output

Delay 1

OUT, OUT1, OUT2 delay relative to

—

150

200

ns

input

Start-Up Self-Cal Delay (t CAL ) 1

Time from VDD = V UVLO + V HYST to

—

150

200

μs

cal complete

Input Common Mode Voltage Range

(dc) 1

4x4 mm QFN

SOIC-20

1000

5000

—

—

—

—

V RMS

V RMS

Operating Input Frequency Range

DC Power Supply Rejection Ratio

Sensitivity @ VDD = 3 V

Sensitivity @ VDD = 5 V

(f) 1

Si8501/11/17

Si8502/12/18

Si8503/13/19

Si8501/11/17

Si8502/12/18

Si8503/13/19

50

—

—

—

—

—

—

—

—

40

404

202

101

392

196

98

1000

—

—

—

—

—

—

—

kHz

db

mV/A

mV/A

mV/A

mV/A

mV/A

mV/A

Notes:

1. Guaranteed by design and/or characterization.

2. Maximum output load is not recommended to exceed 200 pF and 5 k ? .

3. Production tested at 400 kHz (50% duty cycle) at VDD = 3.3 V.

4. See "2.4. Total Measurement Error" on page 11 for more information.

4

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